1. Field of the Invention
The present invention relates to an information processing system having a plurality of input/output devices and a plurality of processors.
2. Description of the Related Art
In the prior art, it is known to provide an information processing system, such as a communications control system or switching system, comprising a plurality of processors and thus designed to distribute a processing load among them. It is desired that such an information processing system be able to readily handle system changes resulting from a system expansion, etc. and various other changes being made while the system is in operation.
In the prior art information processing system, however, associations between the processors and input/output devices or network devices and between the processors and terminals or highways are fixedly defined. This leads to the problem that, when an input/output device is added or removed, for example, extra work for bus reconnection, etc. becomes necessary to accommodate the change in the processor mapping. Furthermore, in the prior art, since the association between the processors and terminals or highways is fixedly defined and is next to impossible to change, the association has had to be established by predicting the amount of control, etc. on the terminals or highways when constructing the system. That is, the prior art configuration has had the problem that processor load sharing, etc. cannot be addressed flexibly once the system is put in operation.
It is an object of the present invention to provide an information processing system wherein associations with the processors can be changed flexibly with a relatively simple configuration.
According to the present invention, there is provided an information processing system comprising: a plurality of input/output devices each having a plurality of input/output terminals; a plurality of processors; and a device controller, provided between the input/output devices and the processors, for storing mapping data defining a mapping of the input/output devices and input/output terminals to the processors and state data indicating states of the input/output devices, terminals, and processors, and for controlling transfer of transmit/receive information from the input/output devices and input/output terminals to the processors and vice versa by referring to the mapping data and the state data.